The present invention relates to a variable length code (hereafter abbreviated as VLC) decoder which can decode the VLC with a sufficient speed and, at the same time, with an appropriate circuit size to be integrated on an IC chip.
In conventional VLC decoders, there are a type having a decode table implemented with random logic circuits such as AND/OR gates, and a type having a decode table implemented on a memory device. Hereafter, the former type will be called a fixed hard type and the latter type, a programmed type.
In the programmed type VLC decoders, there is a decoder which decodes the VLC code by code, a decoder which decodes two codes at once by performing two-stage retrieval of the decode table and determining the beginning bit of a next VLC sequence from addition of code lengths of the two decoded codes, or a circuit which uses a plurality of decode tables for realizing a high-speed decoding, whereof an example is disclosed in a U.S. Pat. No. 5,617,089.
FIG. 9 is a block diagram illustrating a conventional example of the above fixed hard type VLC decoder making use of a decode table implemented with random logic circuits. In the example of FIG. 9, assuming the maximum code length of the VLC as 16 bits, a bit sequence of 16 bits is expressed as 15-0, a numeral 15 representing a beginning bit thereof.
The VLC decoder of FIG. 9 comprises a VLC delimiter 201 for determining beginning of a next bit sequence of the VLC and a random logic decode table 202 consisting of random logic circuits.
The random logic decode table 202 is composed of logic circuits such as AND/OR gates so as to output a decoded word 20B of 8 bits and a code length data 20C of 5 bits which are corresponding to a VLC included in beginning part of an input bit sequence of 16 bits. For example, when a VLC of a decoded word `A` is `0101` and a VLC of a decoded word `B` is `0110 101`, the random logic decode table 202 outputs a decoded word `A` and a code length of 4 when a 16 bit sequence beginning with `0101 . . . ` is supplied, and outputs a decoded word `B` and a code length of 7 when a 16 bit sequence beginning with `0110 101 . . . ` is supplied.
Initial value of delimiting point of the VLC delimiter 201 is set just before the beginning bit.
Suppose a VLC bit sequence 20A of `0101 0110 1010 01 . . . ` is supplied to be decoded.
The delimiting point being set before the beginning bit, the VLC delimiter 201 sends first 16 bits of `0101 0110 1010 01 . . . ` of the VLC bit sequence 20A to the random logic decode table 202. The random logic table 202, which is designed to output the decoded word 20B of `A` and the code length 20C of 4 to the input 16 bits of `0101 . . . `, outputs the decoded word 20B of `A` and the code length 20C of 4. The code length 20C is fed back to the VLC delimiter 201. From the code length 20C of 4, the VLC delimiter 201 sets the delimiting point before the fifth bit of actually decoding VLC bit sequence 20A of `0101 0110 1010 01 . . . `, sends 16 bits of `0110 1010 01 . . . ` beginning with the fifth bit to the random logic decoder table 202, and shifts the VLC bit sequence 20A by 4 bits, rejecting the beginning 4 bits.
The random logic decode table 202, which is designed to output the decoded word 20B of `B` and the code length 20C of 7 to the input 16 bits of `0110 101 . . . `, outputs the decoded word 20B of `B` and the code length 20C of 7, which is fed back to the VLC delimiter 201. From the code length 20C of 7, the VLC delimiter 201 sets the delimiting point before the eighth bit of actually decoding VLC bit sequence 20A of `0110 1010 01 . . . `, sends 16 bits of `001 . . . ` beginning with the eighth bit thereof to the random logic decode table 202, and shifts the VLC bit sequence 20A by 7 bits, rejecting the former 7 bits.
By repeating above procedure, the VLC decoding is performed in the VLC decoder of FIG. 9.
FIG. 10 is a block diagram illustrating a conventional example of the programmed type VLC decoder which decodes the VLC code by code. In the example of FIG. 10, the maximum code length of the VLC is also assumed to be 16 bits and a bit sequence of 16 bits is expressed as 15-0, a numeral 15 representing a beginning bit thereof.
Similarly to the VLC decoder of FIG. 9, the VLC decoder of FIG. 10 comprises a VLC delimiter 201 for determining beginning of a next bit sequence of the VLC and a memory decode table 212.
FIG. 11 is a schematic diagram illustrating data prepared in the memory decode table 212. As illustrated in FIG. 11, when a bit sequence beginning with a VLC code is input as an address of the memory decode table 212, data registered in the address is output as the decoded word 20B and the code length 20C. For example, when a VLC of a decoded word `A` is `0101` and a VLC of a decoded word `B` is `0110 101`, the memory decode table 212 outputs a decoded word `A` and a code length of 4 when a 16 bit sequence beginning with `0101 . . . ` is supplied as the address, and outputs a decoded word `B` and a code length of 7 when a 16 bit sequence beginning with `0110 101 . . . ` is supplied.
Initial value of delimiting point of the VLC delimiter 201 is set before the beginning bit.
Suppose a VLC bit sequence 20A of `0101 0110 1010 01 . . . ` is supplied to be decoded.
The delimiting point being set before the beginning bit, the VLC delimiter 201 sends first 16 bits of `0101 0110 1010 01 . . . ` of the VLC bit sequence 20A to the memory decode table 212. The memory decode table 212, wherein the decoded word 20B of `A` and the code length 20C of 4 are registered in addresses beginning with `0101 . . . `, outputs the decoded word 20B of `A` and the code length of 4. the code length 20C is fed back to the VLC delimiter 201. From the code length 20C of 4, the VLC delimiter 201 sets the delimiting point before the fifth bit of actually decoding VLC bit sequence 20A of `0101 0110 1010 01 . . . `, sends 16 bits of `0110 1010 01 . . . ` beginning with the fifth bit thereof to the memory decode table 212, and shifts the VLC bit sequence 20A by 4 bits, rejecting the beginning 4 bits.
The memory decode table 212, wherein the decoded word 20B of `B` and the code length 20C of 7 are registered in addresses beginning with `0110 101 . . . `, outputs the decoded word 20B of `B` and the code length 20C of 7, which is fed back to the VLC delimiter 201. From the code length 20C of 7, the VLC delimiter 201 sets the delimiting point before the eighth bit of actually decoding VLC bit sequence 20A of `0110 1010 01 . . . `, sends 16 bits of `001 . . . ` beginning with the eighth bit thereof to the memory decoder table 212, and shifts the VLC bit sequence 20A by 7 bits, rejecting the former 7 bits.
By repeating above procedure, the VLC decoding is performed in the VLC decoder of FIG. 10.
A concrete example of the VLC decoder of FIG. 10 is disclosed in a Japanese patent application laid open as a Provisional Publication No. 66720/'87, wherein the VLC delimiter 202 is realized with a data register, code registers, address selectors, a beginning bit register and a control circuit, and the memory decode table is realized with a ROM.
FIG. 12 is a block diagram illustrating another conventional example of the programed type VLC decoder for decoding the VLC code by code, wherein VLC decoding is performed by way of a memory decode table implemented with a reduced memory space.
The VLC decoder of FIG. 12 comprising;
a latch circuit 221,
a selector 222 for selecting either lower three bits (A0) of eight bits output of the latch circuit 221 or second to fourth three bits (A1) of a VLC bit sequence 22A, according to a select signal 22E,
a memory decode table 223 wherein a first bit of the VLC bit sequence 22A is input as a lowest bit (AL) of address data, three bits output of the selector 222 are input as second to fourth lower bits (AHL) of the address data, and upper five bits of the eight bits output of the latch circuit 221 are input as upper five bits (AHH) of the address data, and
a VLC delimiter 224.
The latch circuit 221 latches eight bits (QD) output of the memory decode table 223 when logic of a flag 22D (QF) output from the memory table 223 is `0`.
The memory decode table 223 outputs the flag 22D of logic `1` when the output eight bits (QD) are indicating a decoded word 22B, while outputting the flag 22D of logic `0` when the eight bits (QD) are indicating pointer data.
FIG. 13 is a schematic diagram illustrating data prepared in the memory decode table 223 of FIG. 12.
Referring to FIGS. 12 and 13, decoding procedure of a VLC `0101` representing a decoded word `A` and a VLC `1101 0001 01` representing a decoded word `C` will be described by way of example. The maximum code length of the VLC is assumed to be 16 bits.
The VLC decoder of FIG. 12 can be controlled to analyze the VLC code bit by bit or four bits by four bits according to the select signal 22E. Here, the decoding procedure is described to be performed four bits by four bits.
A VLC bit sequence 22A of `0101 0110 1010 01 . . . ` is supplied to be decoded to the VLC delimiter 224. The VLC delimiter 224 detects the beginning bit of the VLC bit sequence 22A in the same way with the VLC delimiter 201 previously described, and outputs the VLC bit sequence 22A either bit by bit or four bits by four bits at every clock according to the select signal 22E. Here, the VLC delimiter outputs beginning four bits `0101` of the VLC bit sequence 22A.
Initially, the latch circuit 221 is reset and outputs eight bits of `0000 0000`, whereof upper five bits are supplied to the memory decode table 223 as the upper five bits (AHH) of its address data. Lower three bits are supplied to the selector 222, which (A0) is not selected here, in this case.
The beginning bit of the four VLC bits output from the VLC delimiter 224 is supplied to the memory decode table 223 as the lowest bit (AL) of the address data. Second to fourth bits of the four VLC bits are supplied to the memory decode table 223 as second to fourth lower bits of the address data (AHL) selected by the selector 222.
Thus, address data `0000 0101 0` is supplied to the memory decode table 223.
In the address `0000 0101 0`, the decoded word 22B of `A` and the code length 22C of 4 are stored as shown in FIG. 13. In the same way as this example, in every address composed of a pointer, which is fifth to ninth bits (5-8) of the nine bit (0-8) address, of `0000 0`, and one of 1 to 4 bit codes of the VLC as lower four bits (0-3) thereof, the decoded word 22B and the code length 22C of each corresponding 1 to 4 bit code is stored together with a bit data (QF) `1` of the flag 22D, in the memory decode table 223 of FIG. 13, when it is prepared to be used for decoding four bits by four bits.
Returning to FIG. 12, supplied with the address `0000 0101 0`, the memory decode table 223 outputs the decoded word 22B or `A`, the code length 22C of 4 and the flag 22D of `1`. With the flag 22D of `1`, the latch circuit 221 is reset and the VLC delimiter 224 outputs begining four bits of the following VLC bit sequence 22A of `1101 0001 01 . . . `, detecting a four bit VLC is decoded, by the flag 22D of `1` and the code length 22C of 4.
Being reset by the flag 22D of `1`, the latch circuit 221 outputs `0000 0000`, whereof upper five bits are supplied as the upper address AHH of the memory decode table 223. As the lower address AHL and AL, the four VLC bits output from the VLC delimiter 224 are supplied in the same way as above described. Hence, an address `0000 0101 1` is input to the memory decode table 223.
In the address `0000 0101 1` of the memory decode table 223, pointer data (0-7) of `0000 1000` and flag data (QF) of `0` are stored and output. In the same way as this example, in the addresses having lower four bits which cannot identify any VLC code together with its pointer, namely, the upper five bits of the address, eight bit pointer data indicating a next pointer by its upper five bits is stored together with flag data (QF) of `0`.
By the flag 22D of `0`, the output (QD) of the memory decode table 223 is known to be a pointer data, and analysis of the VLC code is continued with next four VLC bits supplied from the VLC delimiter 224.
The eight bit pointer data, that is, the output (QD) of the memory code table 223, is latched by the latch circuit 221. Upper five bits `0000 1` thereof are supplied to the memory decode table 223 as the upper address AHH. The next four VLC bits of `0001`, that is, fifth to eighth bits of the actually decoding VLC bit sequence 22A of `1101 0001 01 . . . `, are supplied as the lower address AHL and AL. Thus, an address `0000 1100 0` is supplied to the memory decode table 223.
In the address `0000 1100 0`, another eight bit (0-7) pointer data of `0001 0000` is stored with a flag data (QF) of `0` to be output. Therefore, the analysis of the VLC code is continued with third four VLC bits supplied from the VLC delimiter 224.
The pointer, that is, upper five bits `0001 0` of the eight bit pointer data, are supplied as the upper address AHH and the 9-12th bits of `01 . . . ` of the actually decoding VLC bit sequence 22A of `1101 00010 1 . . . ` are supplied as the lower address AHL and AL of the memory decode table 223, which gives an address `0001 0xx1` and the decoded word 22B of `C` and the code length of 10 are output with the flag 22D of `1`. With the flag 22D of `1`, the latch circuit 221 is reset to verb/`0000 000`/, and the VLC delimiter 224 delimits the VLC bit sequence 22A according to the code length 22D of 10.
Repeating above procedure, four bits by four bits, the VLC decoding is performed in the VLC decoder of FIG. 12.
When the decode procedure is performed four bits by four bits, upper five bits of the eight bit pointer data are used as the next pointer, lower three bits being ignored by the selector 222. This means that a nine bit address is represented by a pointer of five bits. However, the number of the data sets of lower four bits, for example, of the address data which cannot identify any VLC code together with a pointer, is limited within a certain number which is depending on each coding system of the VLC. Therefore, on condition that the pointer of every analyzing step of the four VLC bits can be represented by one different set of five bits, the memory space of the memory decode table 223 of the VLC decoder of FIG. 12 can be reduced, into 1/2.sup.5 in the example of FIG. 13, compared to the memory decode table 212 of FIG. 11.
When the pointer needs eight bits, for example, data in the memory decode table 223 may be prepared according to a decoding tree for analyzing the VLC bit by bit, making use of all of the eight bits of the pointer data (0-7) as the pointer. The selector 222 is controlled to select lower three bits (A0) of the output of the latch circuit 221, and the VLC delimiter 224 is controlled, by the select signal 22E, to output the VLC bit sequence 22A bit by bit at each clock.
In other words, when the pointer of substantially five bits is sufficient, the memory space of the memory decode table 223 can be still reduced into 1/2.sup.3, by performing the VLC analysis bit by bit, ignoring upper three bits of the address data of the memory decode table 223.
As above described, making use of a tree searching technique, memory space of the memory decode table can be reduced. However, it takes several clocks for decoding a VLC whereof the code length is longer than a searching unit.
FIG. 14 is a block diagram illustrating another conventional example of the programmed type VLC decoder for decoding the VLC by two codes at once.
Referring to FIG. 14, the VLC decoder comprises a first and a second VLC delimiter 231 and 232, a first and a second decode table 233 and 234 each for outputting a decoded word 23B or 23E of eight bits, a code length 23C or 23F of five bits, for example, and a flag 23D or 23G, a first and a second adder 235 and 236, and a pointer circuit 237.
Assuming the maximum code length of the VLC to be 16, a VLC bit sequence 23A or 32 bits (31-0; 32-th bit representing the beginning bit) are supplied at once to the VLC decoder of FIG. 14.
FIG. 15 is a schematic diagram illustrating an example of the first or the second decode table 231 or 232. The first and the second decode table 231 and 232 has similar configuration to the memory decode table 212 of FIG. 11. However, when a part of a VLC code is supplied as its address data, the first or the second decode table 231 or 232 outputs the code length 23C or 23F of 0 and a flag 23D or 23F of of `1`, which becomes `0` when the address data includes full bits of any VLC.
In the example of FIG. 15, a VLC code `0101` is assigned to a decoded word `A`, `0110 01` is assigned to a decoded word `B`, `0111 0101 001` is assigned to a decoded word `C`, and `1011 0100 00` is assigned to a decoded word `D`. Therefore, when an address data beginning with `0101 . . . ` is input, the decoded word `A`, the code length 4 and the flag `0` are output. In the same way, to an address data `0110 101 . . . `, the decoded word `B`, the code length 7 and the flag `0` are output; to an address data `0111 0010 1100 1`, the decoded word `C`, the code length 13 and the flag `0` are output; and to an address `1011 0100 00 . . . `, the decoded word `D`, the code length 10 and the flag `0` are output.
When a part `1011 0100` (eight bits) of the VLC code `1011 0100 00` (code length 10) of the decoded word `D` is input, for example, the first or the second decode table 233 or 234 outputs a code length 0 and a flag `1`, as follows, for example. When an address data shorter than 16 bits is given, the first or the second decode table 233 or 234 is accessed by supplementing lower bits with necessary number of `0`, and when the address data length is shorter than the code length stored in the address, the code length of `0` and the flag `1` are output ignoring the obtained decoded word, otherwise outputting the obtained decoded word and the code length with the flag of `0`.
Now, operation of the VLC decoder of FIG. 14 is described.
Initially, output of the pointer circuit 237 is set to `0` and the first VLC delimiter 231 sets the delimiting point at the beginning bit of the VLC bit sequence 23A of 32 bits.
When a VLC bit sequence 23A of `0101 0110 1010 1110 0101 1001 1011 0100 0001 1010 1 . . . ` is to be decoded, it is supplied to the first VLC delimiter 231. The first VLC delimiter 231, wherein the delimiting point is set at the beginning bit, outputs the first 32 bits `0101 0110 1010 1110 0101 1001 1011 0100` of the VLC bit sequence 23A, which (the first 32 bits) are also supplied to the second VLC delimiter 232, and upper 16 bits thereof, that is, `0101 0110 1010 1110` are supplied to the first decode table 233.
The first decode table 233, wherein data of the decoded word of `A`, the code length of 4 and a flag `0` are stored in the addresses beginning with `0101`, outputs the first decoded word 23B of `A`, the code length 23C of 4 and a flag 23D of `0`. The code length 23C of 4 is sent to the second VLC delimiter 232 and the first adder 235. By the code length 23C of 4, the second VLC delimiter 232 delimits the first 32 bits between the fourth and the fifth bit thereof, and 16 bits `0110 1010 1110 0101` beginning with the fifth bit of the first 32 bits are supplied to the second decode table 234.
The second decode table 234, wherein data of the decoded word of `B`, the code length of 7 and a flag `0` are stored in the addresses beginning with `0110 101 . . .`, outputs the second decoded word 23E of `B`, the code length 23F of 7 and the flag 23G of `0`. Th code length 23F of 7 is sent to the first adder 235.
The first adder 235 adds the code length 23F of 7 to the code length 23C of 4 (corresponding to the decoded word `A`). Output 4+7=11 of the first adder 235 is sent to the second adder 236 and added to output of the pointer circuit 237. The output of the pointer circuit 237 being initialized to be 0, here, 11+0=11 is output from the second adder 236, which is supplied to the first VLC delimiter 231 through the pointer circuit 237. With the output of 11 of the pointer circuit 237, the beginning bit of the next VLC code is detected to be the 12th bit of the first 32 bits by the first VLC delimiter 231. Hence, 16 bits `0111 0010 1100 1101` beginning with the 12th bit of the first 32 bits are supplied to the first decode table 233, and 21 bits from 12th to 32th bits `0111 0010 1100 1101 1010 0` of the first 32 bits are sent to the second VLC delimiter 232.
The first decode table 233, wherein the decoded word `C`, the code length 13 and the flag `0` are stored in the addresses `0111 0010 1100 1 . . . `, outputs the first decoded word 23B of `C`, the code length 23C of 13 and the flag 23D of `0`. The code length 23C of 13 is sent to the second VLC delimiter 232 and the first adder 235. By the code length 23C of 13, the second VLC delimiter 232 delimits the second 21 bits between the 13th and 14th bit thereof, and 8 bits `1011 0100` beginnings with the 14th bit of the second 21 bits are supplied to the second decode table 234. The second decode table 234, which is configured to output the code length 23F of 0 and the flag 23G of `1` when address data length is shorter than the code length, sends the code length 23F of 0 to the first adder 235 and the flag 23G of `1` to the first VLC delimiter 231.
The first adder 235 adds the code length 23F of 0 to the code length 13 corresponding to the decoded word `C` and sends 13+0=13 to the second adder 236. The second adder 236 adds 13 output from the first adder 235 to the output of 11 of the pointer circuit 237, which (13+11=24) is sent to the pointer circuit 237 and supplied to the first VLC delimiter 231. With the revised output of the pointer circuit 237 of 24, the first VLC delimiter 231 detects that a next VLC code begins from 25th bit of the VLC bit sequence 23A of `0101 0110 1010 1110 0101 1001 1011 0100 0001 1010 1 . . . `.
The flag 23G of `1` is also sent to the first VLC delimiter 231, indicating that the 8 bits supplied to second decode table 234 is not sufficient to be decoded. Therefore, the first VLC delimiter 231 outputs next 32 bits `1011 0100 0001 1010 1 . . . ` beginning with the 25th bits of the VLC bit sequence 23A. The output of the second decode table 234 is ignored when the flag 23G of `1` is output.
By repeating above procedure, the VLC decoding is performed by the VLC decoder of FIG. 14.
FIG. 16 is a block diagram illustrating another conventional example of the programmed type VLC decoder for decoding two codes at once, such as disclosed in the previously mentioned U.S. Pat. No. 5,617,089, In FIG. 16, the maximum code length of the VLC is assumed also to be 16 bits.
The VLC decoder of FIG. 16 comprises;
a VLC delimiter 241,
a first to 17th decode table 242 to 258, whereof each i-th (i=1, 2, . . . , 17) is supplied with 16 bits beginning with i-th bit of a VLC bit sequence 24A after delimited by the VLC delimiter 241, and
a selector 259 for selecting output data of one of the second to the 17th decode table 243 to 258 according to a code length 24C obtained from the first decode table 242.
FIG. 17 is a schematic diagram illustrating configuration of the first to the 17th decode table 242 to 258. The first decode table 242 has substantially the same configuration with the memory decode table 212 of FIG. 11, and the second to the 17th decode table 243 to 258 have similar configuration to the first decode table 242.
The only difference of the second to the 17th decode table to the first decode table 242 is that a total code length is stored in place of the code length of each address of the first decode table 242, said total code length indicating (Total code length)=(Code length)+(Order number of each decode table)-1.
For example, when a VLC code `0101` is assigned to a decoded word `A`, the decoded word of `A` and the code length of 4 are stored in the addresses beginning with `0101 . . . ` of the first decode table 242. In the same addresses, the decoded word of `A` and the total code length of 5 are stored in the second decode table 243, and the decoded word of `A` and the total code length of 4+i-1 are stored in the i-th decode table.
Now, operation of the VLC decoder of FIG. 17 is described.
When the delimiting point is set at the beginning, a VLC bit sequence 24A `0101 0110 1010 0100 1 . . . ` supplied to the VLC delimiter 241 is output as it is, whereof 16 bits `0101 0110 1010 0100` beginning from the first bit (31-16) are supplied to the first decode table 242, and each 16 bits (30-15), (29-14), . . . , (15-0), beginning from the second, third, . . . , 17th bit, are supplied to each of the second to the 17th decode table 243 to 258, respectively, as illustrated in FIG. 17.
The first decode table 242, wherein the decoded word `A` and the code length 4 are stored in the addresses `0101 . . . `, outputs the first decoded word 24B of `A` and the code length 24C of 4. Each of the second to the 17th decode table 243 to 258 outputs some data stored in the address supplied thereto.
However, the selector 259 selects data output from the (i+1)-th decode table when the code length 24C output from the first decode table 242 is i. Here, in this case, the code length is 4. Therefore, the outputs of the fifth decode table 246 are selected.
The fifth decode table 246, wherein 16 bits (27-12) beginning from the fifth bit of the VLC bit sequence, that is, `0110 1010 0100 1 . . . `, are supplied and the decoded word `B` and the total code length 11 are stored in the addresses `0110 101 . . . `, outputs the second decoded word 24D of `B` and the total code length 24E of 11.
Thus two codes are decoded at once.
The total code length 24E of 11, which indicating a sum of the code length corresponding to the decoded word `A` and that corresponding to the decoded word `B`, is fed back to the VLC delimiter 241 to be used for delimiting next 32 bits of the VLC bit sequence 24A. In this case, the VLC decoder 241 outputs the next 32 bits `0010 01 . . . ` beginning from the 12th bit of the VLC bit sequence 24A.
By repeating the above procedure, the VLC decoder of FIG. 17 performs the VLC decoding two codes by two codes.
FIG. 18 is a block diagram illustrating still another example of a conventional VLC decoder to be applied for decoding so called B2-code.
The VLC decoder of FIG. 18 comprises a bit shifter 261 for delimiting a VLC bit sequence 26A of the B2-code system, by shifting according to a shift number 26I, a code length decoder 262 for obtaining the code length 26D from continuation bits included in the B2-codes, a lookup table 263 for outputting decoded data 26E, a zero-run flag 26F, an EOB flag 26G and an EOB0/EOB1 flag 26H by decoding the B2-codes from information bits included in the B2-codes and the code length 26D.
According to the B2-code system, a maximum code length is defined to be 18, for example, and composed of a pair of continuation bit and an information bit when the code length is not 18 bits. A B2-code ends at an information bit following a continuation bit of `0`, or 18th bit from the beginning. Therefore, the 17th bit is used as the ninth information bit when the code length is 18.
Making use of this characteristic of the B2-code system, 18 bits of the VLC bit sequence 26A delimited by the bit shifters 261 is divided into 10 information bits 26B and 8 continuation bits 26C. From position of `0` bit in the 8 continuation bits, or the fact there is no `0` bit, the code length 26D is decoded by the code length decoder 262. The lookup table 263 decodes the 10 information bits 26B instead of 18 bits of the possible VLC code length and outputs the decoded data 26E, the zero-run flag 26F, the EOB flag 26G and the EOB0/EOB1 flag 26H referring to the code length 26D.
The code length 26D is accumulated by the latched circuit 265 and the adder 264 on the shift number 26I and used by the bit shifter 261 for delimiting the VLC bit sequence 26A.
Heretofore, some examples of the conventional VLC decoders are described. However there are merits and demerits in these conventional VLC decoders.
The fixed hard type VLC decoder having a decode table realized with random logic circuits, such as described in connection with FIG. 9, every VLC code can be decoded by one clock. However, it can not be used except for decoding the VLC encoded according to a specific VLC coding system, without re-designing the decode table, that is, the hardware itself.
As to the programmed type VLC decoder for decoding code by code, such as described in connection with FIG. 10, it can be adapted to various VLC coding systems by re-writing data of the memory decode table. However, the memory decode table needs a large memory space, a memory space of 64K words, for example, when the maximum code length of the VLC is 16 bits, which is difficult to be integrated on an IC chip.
In the programmed type VLC decoder such as described in connection with FIG. 12 for analyzing the VLC code bit by bit or four bits by four bits making use of the tree searching technique, the memory space of the memory decode table can be reduced. However, it takes several clocks for decoding a VLC. Therefore, sufficient decoding speed cannot be obtained, especially for decoding compressed video data such as MPEG (Moving Picture Experts Group) data which must be described in real-time.
For improving the decoding speed, the VLC decoder for decoding two codes at once is somewhat effective. However, the circuit configuration such as described in connection with FIG. 14 needs a long path starting from the first VLC delimiter 231 and returning there through the first code table 233, the second delimiter 232, the second decode table 234, the first adder 235, the second adder 236 and the pointer circuit 237. Therefore, the clock frequency is limited within a value, and doubled memory space is needed for two decode tables.
The VLC decoder of FIG. 17 has no problem of the long path. However, enormous memory space is needed for 17 decode tables.
The VLC decoder of FIG. 18, a high speed decoding may be performed with a comparatively small memory space by extracting the information bits from the VLC code. However, it cannot be applied but to the VLC code according to a special coding system such as the B2-code.